1. Field of the Invention
The present invention is directed to the reduction of coupled noise in parallel conductors on circuit boards or integrated circuit modules.
2. Related Art
High performance integrated circuit packages, and in particular in packages having multilayer printed circuit boards or substrates, wiring planes typically include a number of closely disposed conductors lying parallel to one another. Continual effort is being expended to form insulated packages carrying conductors in greater numbers. This is often accomplished by providing conductors having smaller cross sections and closer center-to-center spacing. In multilayer substrates, an increase in conductors is also commonly provided by increasing the number of layers of circuits per unit thickness.
As conductor density increases, in the various levels of packaging such as VLSI chips, chip carriers, circuit cards and boards, the problem of coupled noise or cross talk among conductors assumes greater prominence. This noise results from voltages induced in a quiet conductor by the switching of currents in other, parallel, nearby energized conductors. The adversely effected conductors lie within a proximity region whose effective radius from an energized conductor varies with with signal frequency, parasitic capacitance, inductance, source and termination impedance, dielectric constant, distance to ground and voltage plane, extent of conductor parallelism and other factors. As more conductors are placed within a volume, high frequency switching induces voltage levels that can be falsely detected as data, resulting in processing errors.
The prior art includes a number of methods for reducing coupled noise between parallel conductors. Examples of prior art solutions include reducing conductor size to enlarge separation, decreasing dielectric constant of insulators or placing ground reference planes nearby. While each of these solutions provides some degree of relief, each has its problems. For example increasing the separation distance of conductors on a given plane may decrease the achievable wiring density. Further, since closely disposed conductors lying in parallel to one another are subject to cross talk, whether in the same or adjacent planes, the distance between neighboring conductors on a given plane may not be the dispositive factor in providing an acceptable signal to noise ratio. The use of ground planes between signal planes, while helpful, adds to the expense of fabrication and, in any event, does not completely dispose of the cross talk between conductors on the same substrate layer. Further, while combinations of these solution can be implemented, this may still not be sufficiently improve the signal to noise ratio in conductors operating at low voltages.
U.S. Pat. No. 4,785,135 to Ecker et al. describes an arrangement for reducing cross talk between electrical circuit conductors wherein conductors lying within each others induced voltage or cross talk region are arranged in parallel or common substrate channels so as to converge or diverge with respect to one another. A problem with Ecker is that shifting conductors from their normal parallel locations adds a complicating factor for wiring layout calculations.
U.S. Pat. No. 5,006,918 to Deutsh et al. describes an arrangement wherein far end wiring noise caused by coupling between active and quiet signal lines of wiring planes of an integrated circuit chip or chip carrier is reduced by providing floating crossing lines in wiring layers in an X-Y wiring plane pair. While Deutsh deals with the reduction of far end noise, other factors, for example near end noise, can also cause significant problems.
Thus, there is a need to further reduce coupled noise between conductors on multilayer circuit boards.